IC Test & Analysis Seminar

11 May 2015

MASER Engineering B.V. and MICL Group Consulting and Logistics Ltd. are proud to present:

IC Test & Analysis Seminar

Failure Analysis and Reliability Test
Services, Tools and Technology update

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Monday May 11th, 2015
AVENUE Convention and Event Center
Hasharon Street 1, Airport City, Tel Aviv, Israel


8:30 Registration
9:00 Welcome and Opening
Eldad Keren - CEO of MICL group
9:15 Non Destructive Analysis
Kees Revenberg - Co-founder and CEO of MASER Engineering
In case of a defect electronic component or module, the first fault confirmation is an electrical test. This introduction will highlight other non-destructive analysis techniques and their typical applications: XRAY microscopy, 3D XRAY tomography, Ultrasound microscopy, Thermal Lock-In analysis and Electro-Optical THz Pulse Reflectometry.
10:00     Sample Preparation Techniques and Tools
Shachar Bard – Sales and Application Engineering MICL
The next steps in Failure Analysis require controlled sample preparation. The removal of plastic material in order to get optical access to the chip(s) inside is nowadays a combination of laser ablation, mechanical and chemical processing. The latter became more complex due to the use of Copper wires. The Nisene solution for this task will be presented.
Planar mechanical polishing is a common technique to remove the top metal interconnections or to thin the die for backside F/A processing. This presentation shows the current state of art in these preparation tools based on Allied tools.
10:30 Coffee / Tea break
11:00 Electrical Fault Localization: Key for Fast Yield Ramp
Dr. Israel Niv – Founder and CEO of DCG Systems Inc.
Electrical faults are the main cause for yield problems of new IC products using advanced processes. These faults are usually not detected by the current process control systems. Electrical faults (also called non-visual defects) are manifested when the IC manufacturing is completed and the IC device fails the electrical test. In this presentation DCG will present customers’ work flow and case studies of using the various DCG products to localize the electrical fault which leads to root cause identification and corrective actions.
12:00 Lunch break
13:00 Panel Session – System In Package impact for F/A
Moderator: Dr. Yoav Weizman – Director at enICs institute BIU
Dr. Israel Niv – DCG Systems Inc.
tba – enICs institute at Bar Ilan University
Kees Revenberg – MASER Engineering
This panel session is a discussion with the audience about the impact of System In Package assembly of high-end modules on Failure Analysis and Reliability Test aspects. The panel members will give their view on the necessary adaption of the F/A lab tool kit for handling these SIP assemblies. The audience is stimulated to contribute actively in the discussion.
14:00 ESD/LU Test and Reliability Qualification Test
Kees Revenberg – Co-founder and CEO of MASER Engineering
New chip designs have to be validated before mass production can start. In most cases, the ESD/LU behavior is characterized. Further reliability qualification test procedures depend on the application and/or customer requirements. This presentation gives an overview of the most common test methods.
15:00 Coffee / Tea break
15:30 Circuit Edit and Defect Imaging
Dr. Peter de Veen – R&D Manager of MASER Engineering
This presentation is a working practice on Circuit Edit services on state-of-the-art first silicon. The DCG OptiFIB IV at MASER Engineering can handle both front and backside edits.
In the F/A flow, sample preparation and fault localization is in an iteration process with optical, electron and ion beam, and scanning probe microscopy. The SEM/TEM/HIM/FIB/AFM systems are an essential toolkit for defect imaging, to conclude the Failure Analysis.
16:30 Q&A and i-Pad mini raffle
17:00 End of Seminar

Photo impression

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Monday May 11th, 2015


AVENUE Convention and Event Center
Hasharon Street 1, Airport City, Tel Aviv, Israel

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MICL group, Ramat Gavriel, Hataasiah street 5
P.O. Box 112, Migdal Haemeq, Israel 23100
Phone: +972 4 834 39 66
Mobile: +972 54 675 55 22

You can download the program booklet of the IC Test & Analysis Seminar here (pdf).