MASER in cover story of EuroAsia Semiconductor Magazine (08-2008)

01 August 2008

In the 2008 August edition of the EuroAsia Semiconductor Magazine (now Silicon Semiconductor Magazine), the cover story is fully dedicated to the new test and diagnostic tools MASER Engineering now has available for their Failure Analysis services.

Below you can read the whole cover story. The original document can be downloaded here.

 

Failure analysis services

New and more advanced equipment can give a company a significant advantage in manufacturing processes. Kees Revenberg of MASER Engineering describes their new test and diagnostic tools.

EuroAsia semiconductor 30 (2008) front small.jpg EuroAsia semiconductor 30 (2008) 15 small.jpg EuroAsia semiconductor 30 (2008) 16 small.jpg

The fabless semiconductor business model creates a constant flow of innovative companies. They are successful in creating new innovative semiconductor applications by focusing on the application design. All their financial strength and manpower is directed towards the integrated circuit design, application software development and product implementation support. A successful acceptance of the new application can create high volume IC sales. Modern high density electronics require advanced manufacturing facilities in the total supply chain. Today, the investment, manpower and know how to integrate this in one company is becoming increasingly prohibitive. Therefore, specialised service providers offer the necessary high tech facilities for advanced CMOS wafer fabrication and device packaging and test. The fabless semiconductor IC manufacturers can outsource their volume manufacturing flow to these service providers. What remains is the control of the flow by product and quality engineers and assurance of product qualification and field return support. The increasing complexity of products however, requires more specialised tools and know how. The same drive to outsource the main IC manufacturing flow is becoming valid for specialized qualification tasks and because of the high cost specialized equipment and capability necessary for failure analysis of 90 nm and below copper CMP technology and for devices with smaller dimensions. The justification of an in house full range IC qualification and F/A lab is getting more difficult. The load of the individual systems is not sufficient for a profitable operation. This has a negative influence on the decision to invest in newer tools in order to stay in line with the device technology. The solution is to outsource qualification test and failure analysis to independent service providers. These ISPs can offer the high end equipment, engineering competence and experience and full independence to give the highest level of unbiased engineering support at the right price.

MASER Engineering has recently expanded their test and diagnostic services with more than 15 advanced tools for test and failure analysis of integrated circuits based on copper CMP technology, low-K dielectric layers and device geometries of 90nm or smaller. These facilities are available including qualified staff of engineers. The expansion of the MASER Engineering test and F/A services addresses four main issues with the new technology nodes:

  • decreasing feature size
  • new materials for conductors and isolators
  • more functions on a chip
  • more complex packaging

Test and diagnostics tools for ESDJLU, qualification and F/A
IC production test is linked to the mainstream output of the assembly line for the specific product. These ATE systems are operated in a 24/7 regime. ATE system access for product engineering, field return analysis or further F/A tasks does not fit in a production environment very well. In several instances, product engineering departments own a dedicated ATE system for test programme development jobs, product engineering and F/A. MASER Engineering is offering both shared ATE access and a Verigy/Inovys Ocelot ZFP test system for structural testing and ATE fault vector simulation during F/A projects. This test system is dedicated for qualification read point testing and failure analysis. Another continuous challenge for the IC design and process engineers is the development of a proper ESD protection. MASER Engineering has expanded the Thermo KeyTek Mk.2 and RCDM line of ESD and Latch-Up test capabilities with automatic test systems for high pin count devices, meeting HBM, MM and CDM standard requirements. MASER Engineering also has a specialised ESD gate leakage test capability. MASER Engineering has built numerous package interfaces for a wide range of customers during the years we are active in ESD/LU testing. The latest addition is a high voltage HBM test system (up to 30kV) for system in a package devices and module testing, meeting upcoming new device test standards. Finally, MASER Engineering has adapted the lower core voltages and need for backside Photon Emission Microscopy and OBIRCH by the extension of the Hamamatsu Phemos 1000 with the second generation Peltier cooled InGaAs camera. This very sensitive NIR camera is the best solution to trace photon emissions through the backside of a chip, where the multiple front side metal layers prevent surface emission.

Non destructive analysis and sample preparation
The new facilities include a new 2D and 3D X-ray inspection system. The Phoenix X-ray nanomex 180CT has become a strong tool in F/A of package related failure modes. Also detailed non destructive inspection of lead free solder interfaces on final product modules has gained from the technological improvements in X-ray tubes and detectors. The complementary non destructive inspection technique uses high frequency ultrasonic sound for another set of package related failure modes. Scanning acoustic microscopy is very sensitive to delaminating layers issues. MASER Engineering expanded the SAM facilities with another system and has now two identical SAMTEC Evolution-II systems of the latest generation available, with reflective and through scan capabilities and a scan frequency range of 10 to 400 MHz. Another set of tools improves the sample preparation techniques. Laser assisted plastic removal, multiple wavelength laser cutting, dual argon beam milling and polishing, single chip chemical mechanical polishing tools and rewiring chips by semi automatic wire bonders are used to get access to the defect die inside these complex packages. Backside preparation of multiple metal layer devices is necessary to get access to the active area for fault localisation techniques.

First silicon circuit edit and FIB service
Being active in FIB services with multiple single column systems for over 12 years, MASER Engineering encountered the end of life of multi function FIB systems. The first generations were used for first silicon circuit edit, site specific cross section and ion Imaging, TEM sample preparation and micro machining of MEMS devices. MASER Engineering decided to replace two of her single beam FIB systems with a dedicated system for front and backside circuit edit applications and a dual beam FIB/FEGSEM system for F/A cross sectioning, imaging and TEM sample preparation. DCG systems (formerly Credence Diagnostics & Characterisation Group) recently installed their first OptiFIBIV system in Europe at MASER Engineering. This system has a unique coaxial NIR optical and Ga+ ion column that allows both front and backside circuit modifications. The high accurate piezo stage with NEXS CAD navigation, new copper etching gas chemistry, molybdenum metal deposition and FIB assist software tools for optimised endpoint detection allow the engineers to modify circuits down to the 45 nm technology node.

Advanced Electron and Ion Microscopy
The smaller feature sizes in semiconductor devices require higher magnifications for proper imaging. Modern field emission gun SEM systems combine high resolution optics and maintain that resolution at decreased acceleration voltages or at variable vacuum environments. The latter features are important for imaging semiconductor layer stacks. The combination of insulators and metal layers in semiconductor devices are susceptible for charging and result in distorted pictures at the nominal 30kV high voltage. MASER Engineering added a high resolution field emission gun electron microscope to its existing SEM base. The FEI NOVA NanoSEM 230 is the latest generation of FEG-SEM systems for imaging and analysis of nano scale devices. The defect areas of interest in ICs quite often is hidden under the surface. Site specific cross sectioning and imaging is necessary. The versatile FEI Quanta 3D FEG system has been installed at MASER Engineering for this application. The system combines a high resolution field emission gun SEM and a FIB column with multiple gas injection needles for deposition and etching. The combination of material removal and high resolution imaging can be automated resulting in a slice and view sequence of the defect area. The Quanta 3D FEG is also equipped with an Omniprobe system for thin lamella lift out. This is the only way site specific TEM samples can be extracted from a semiconductor surface. The 100nm thin slices are mounted on special TEM sample holders inside the vacuum chamber. This reduces the contamination level and improves the reliability by avoiding manual manipulation of these very small and fragile samples. The Quanta 3D FEG is expected to become the core imaging, analysis and preparation tool for the future F/A tasks. To meet the highest resolution in electron microscopy, MASER Engineering added a FEI 200kV TECNAI G2 field emission gun X-TWIN Scanning Transmission Electron Microscope to the available failure analysis equipment list. This system is optimised for EDX analysis with mapping resolutions


Ref.: EuroAsia Semiconductor 30-7 (2008) 15-16