ATHENIS 3D (EU / FP7)

MASER Engineering is participating in the European FP7-funded “ATHENIS 3D” project, which is an abbreviation of “Automotive Tested High Voltage and Embedded Non-Volatile Integrated System on Chip Platform employing 3D integration”. 

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Duration: 3 years (November 2013 - October 2016).

Project Overview

The finished EU/FP7-funded project ATHENIS has successfully addressed System-on-Chip (SoC) integration of CMOS, high voltage and embedded memory for harshest automotive conditions (link). Further cost reduction will require even higher levels of integration.

In the ATHENIS 3D project, a consortium of 11 partners from Austria, France, Italy, Germany and The Netherlands will work together on providing the industry’s first 3D heterogeneous integration technology platform for harshest automotive conditions with Through Silicon Vias (TSV’s) and Wafer Level Packaging (WLP). A demonstrator car will prove the functionality of the 3D integrated electronics for an electrical machine with start/stop function and the industry’s first 3D/TSV/WLP DCDC converter with integrated inductor for the new 48 V standard.

Cost savings from integration and a 5x reduction of PCB area at improved reliability will be shown. For this purpose substantial technological barriers such as flipchip mounting of a 90 nm CMOS FPGA on a 180 nm HVCMOS Si interposer with Integrated Passive Devices (IPD), high density MRAM and magnetic sensors all meeting reliability requirements up to 200 °C application temperatures have to be overcome for the first time. This will be achieved by combining TSV and HV-CMOS technology with CMOS and Cu-TSV technology, MRAM technology and WLP technology. Platform scalability will be proven by flipchip packaging down to 14 nm CMOS samples on the interposer. New modules for TSVs, MRAM, and Passives embedded in TSV technology will be developed to enable 200 °C applications.

Objectives

  • Specify a reliable high-performance and low system cost 3D heterogeneous integration technology platform using TSV and WLP that meets harshest automotive requirements.
  • Define and develop novel key process modules and IP for the ATHENIS 3D platform.
  • Define integration concepts based on automotive system requirements and form the ATHENIS 3D heterogeneous integration technology platform by combination of 0.18 µm HVCMOS with TSV and BRDL, embedded NVM SR-TAS MRAM, IPDs, and stacked nanoCMOS.
  • Develop IP blocks (DCDC converter, BUS systems) and circuit design for the 3D IC demonstrators (demonstrator 1: alternator regulator; demonstrator 2: 48 V DCDC converter) to verify ATHENIS 3D platform capabilities.
  • Develop novel methods for the simulation, characterization and the reliability investigation of the 0.18 µm HVCMOS interposer with SR-TAS MRAM and stacked nanoCMOS and IPDs, including predictive models.
  • Perform system development to help specify the ATHENIS 3D platform and integrate the demonstrators and the ESTRELIA Battery management system (link) in a HEV demo car.

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Contribution MASER Engineering

MASER Engineering will participate in the project in two main areas, reliability testing and failure analysis. The first item consists of implementing new reliability and ESD strategies for the NVM and 3D integrated system on a chip devices and the practical setup development for the robustness approval of the device in applications. The second participation field is in the preparation and implementation of physical failure analysis procedures, tooling and techniques, in order to be prepared for product field returns of NVM and complex 3D integrated devices. 

Project Consortium

  • Active Technologies, Italy (link).
  • ams, Austria (link).
  • BESI, Austria (link).
  • CEA-Leti, France (link).
  • Crocus Technology, France (link).
  • Fraunhofer Gesellschaft, Germany.
    • Institut für Integrierte Schaltungen (FhG IIS), (link).
    • Institut für Integrierte Systeme und Bauelementetechnologie (FhG IISB), (link).
  • MASER Engineering, The Netherlands (link).
  • Technische Universität Wien, Austria.
    • Institute for Microelectronics (link).
  • University of Ferrara, Italy (link).
  • University of Pisa, Italy (link).
  • Valeo Electrical Systems, France (link).

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Links

Project information

  •  ATHENIS 3D project website (link).

Publications

  • Article "A predictive physical model for hot-carrier degradation in ultra-scaled MOSFETs" on SISPAD 2014 (Yokohama, Japan) by Tech. Univ. Wien, Austria [09/11-09-2014] (link).

Press releases

  •  Press release MASER Engineering [16-01-2014] (link).

Funding

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